1. Technical Field
The present invention relates to a memory controller, and more particularly, to a memory controller for controlling a refresh cycle of an external memory and a method thereof.
2. Discussion of the Related Art
In general, data is stored as charges in capacitors located in dynamic random access memory (DRAM) cells. Because the capacitors on which the charges are stored are not perfect, their stored charges leak over time. Thus, a process for reading out data from the DRAM cells and rewriting the data back to the DRAM cells needs to be repeated before the data stored in the capacitors is lost. This process is called a refresh operation.
In principle, computers cannot use DRAMs during the refresh operation. For example, the time required to perform one refresh operation is equal to a cycle time of a common write operation, thus after the time for performing the refresh operation has passed, external computers cannot use the DRAMs. The time during which the DRAMs cannot be used due to the refresh operation is called a busy rate. As such, computers are typically designed to have a busy rate as short as possible. When computer systems are in a sleep mode, most of the systems' internal devices are turned off, while the DRAMs therein are refreshed to maintain their data. Accordingly, a self refresh current flows through the DRAMs. Thus, it is important for battery-operated computer systems to reduce their self refresh current.
A recent trend in the development of computer systems is to change a refresh cycle according to temperature variations and thus reduce the refresh current. For example, a frequency of a refresh clock is lowered by dividing temperatures into several levels from low to high and then using a low temperature to reduce the current consumption of a computer system. This development trend is based on the fact that DRAMs retain data for a longer time when they are subject to lower temperatures.
In system-on-a-chip (SOC) products and/or system-in-a-package (SIP) technology, which involve stacking memory chips, e.g., negative AND (NAND) flash memory chips, synchronous dynamic random access memory (SDRAM) chips, or double data rate (DDR) SDRAM chips in a single package, the heat generated by processors used, for example, in the SOC or SIP products is directly transferred to the memory chips disposed above the processors.
When using the SOC or SIP products, the heat generated during a refresh operation causes DRAMs, which are adversely affected by excess heat, to deteriorate. Thus, a time during which the DRAMs can retain data is reduced due to the heat generated by the processors or circumferential environments. One method used to prevent the deterioration of DRAMs due to excess heat is to assume the worst-case temperature conditions during the design process of the DRAMs, and thus, shorten the auto refresh cycle for the DRAMs.
In addition, as hand-held devices require high-performance and various multi-media functions as well as high speed data communication capabilities, the performance of their DRAMs is also important. Therefore, the SOC or SIP products must also deal with performance degradation resulting from an auto refresh command cycle that has been shortened to compensate for the worst-case temperature conditions.
The above method of shortening the auto refresh cycle is typically the only way to retain the data of the DRAMs when temperatures are at their highest levels, namely, when refresh operations of the DRAMs are in the worst case. However, because the auto refresh cycle of the DRAMs is determined under the worst case, the performance of the DRAMs in the SOC or SIP products deteriorates except when the temperatures are at their highest levels.